1. Field of the Invention
The present invention relates generally to a flash memory and in particular the present invention relates to using a microcrystalline polysilicon film as a floating gate to improve the performance of a flash memory cell.
2. Description of the Prior Art
A typical flash memory comprises a memory array, which includes a large number of memory cells arranged in row and column fashion. Each of the memory cells includes a floating gate field-effect transistor capable of holding charges. The memory cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed in a random basis by charging the floating gate. The charges can be removed from the floating gate by a block erasure operation. The presence or absence of the charges in the floating gate determines the data in a cell.
FIG. 1 is a cross-sectional view of a typical memory cell 5, such as used in a flash memory. The memory cell 5 comprises a region of a source 60 and a region of a drain 70. The source 60 and drain 70 are separated by a predetermined space of a channel region 80. The memory cell 5 further includes a floating gate 30 formed by a first polysilicon layer and a control gate 50 formed by a second polysilicon layer. The floating gate 30 is isolated from the control gate 50 by an interpoly dielectric layer 40 and from the channel region 80 by a thin oxide layer (a tunnel oxide layer) 20 with approximately 100 angstroms thick.
FIG. 2 shows a magnified cross-sectional view of a floating gate of a polysilicon layer 84 formed on a thin oxide layer 82 such as a tunnel oxide. The polysilicon layer 84 is formed by depositing silicon onto the surface of the thin oxide layer 82 in a low pressure chemical vapor deposition (LPCVD) chamber at a temperature of approximately 600° C. by using silane (SiH4) as reaction gas. The grain size of the polysilicon layer is about 1000 angstrom to about 2000 angstrom. The surface roughness of the polysilicon layer 84 is a result of the large-grained columnar crystal structures within the film. This pronounced surface roughness makes it difficult to obtain good patterning profiles due to the significant variation in inter granular thickness of a photoresist layer formed on the surface of the polysilicon layer 84 and the non-uniformity in reflectivity which occurs during the photolithographic process. The non-uniformity in reflectivity of the photoresist layer causes bad etching profiles, and resulting in the polysilicon stringer issue.
FIG. 3 shows a magnified cross-sectional view of another floating gate of a polysilicon layer 88 formed on a thin oxide layer 86 such as a tunnel oxide. The polysilicon layer 88 is formed by a process in which silicon is deposited on the surface of the thin oxide layer in a LPCVD chamber at a temperature of approximately 550° C. By depositing silicon at this lower temperature, amorphous silicon is created because crystal grains cannot develop at this low temperature. This amorphous silicon is subsequently recrystallized by being exposed under a temperature in excess of 600° C. The result is the polycrystalline structure of a polysilicon layer 88 shown in FIG. 3, wherein large crystal grains are formed. While the polysilicon layer 88 of FIG. 3 overcomes the problems associated with surface roughness of FIG. 2 described above. The large grain size of the polysilicon layer 88 reduces the grain boundary density of the film. In addition, because the polysilicon layer 88 is deposited at a low temperature, the deposition rate is quite low, resulting in slow throughput times.
The charge storage or erasure of the flash memory cell 5 as shown in FIG. 1 is programmed by Fowler-Nordheim tunneling of electrons through the thin tunnel oxide layer 20 between the floating gate 30 and the channel region 80. The thin tunnel oxide layer 20 generally is about 100 angstroms. In the programming mode for the flash memory cell 5, hot carriers tunnel from the channel region 80 to the floating gate 30 and are stored in the floating gate 30. The control gate 50 and the drain 70 of the flash memory cell 5 are positively biased while the source 60 is grounded. In the erasure mode, usually programmed, the drain 70 is biased at a high voltage to finish the erasure process.
An over erased memory cell has a faster erasure speed, which means a higher electron current through the thin tunneling oxide layer 20. When using a floating gate formed of large-grained polysilicon causes wider threshold voltage (Vt) distribution. If over erased blocks exist, threshold voltage distribution after erasure has tail components and larger variance values. In other words, the wider threshold voltage distribution corresponds to large polysilicon grains.
In the conventional process for fabricating a flash memory, by using a large-grained polysilicon film as a floating gate. There are many drawbacks such as over erasing, wider threshold voltage distribution, tail bit issue, tunnel oxide quality down, higher polysilicon resistance and bad etching profile due to the polysilicon stringer issue.